1. Field of the Invention
The present invention relates to a DC/DC converter and in particular, to a high-efficiency DC/DC converter using a piezoelectric transformer.
2. Description of the Related Art
Conventionally, this type of technology used four-diode bridge rectification for rectification of a piezoelectric transformer of two-terminal output as a first conventional example described in xe2x80x9cNew Piezoelectric Transformer Converter for AC-adapter,xe2x80x9d IEEE APEC97 (Applied Power Electronics Conference 97), pp. 568-572, FIG. 4 [A]. By using the bridge rectification, both of a positive half cycle and a negative half cycle can supply power to the load.
In the aforementioned FIG. 4 of document [A], if the diode voltage drop in the forward direction is VF, the diode forward direction voltage drop is 2 VF because two diodes are connected in series in each cycle.
On the other hand, as a second conventional example, JP Patent, Publication of Unexamined Application A-7-59338 [B] suggests a piezoelectric transformer having a three-terminal output configuration in which a piezoelectric transformer output block (secondary side) has an intermediate tap for taking out an intermediate voltage so that the rectifier forward voltage drop is VF. When such an intermediate tap is provided, as shown in FIG. 1 of document [B], it is possible to easily constitute a rectifier circuit having a diode forward voltage drop of VF. Moreover, a power source circuit having a current doubler (Double Ended Converter using Two Inductors) is disclosed in US Pat. No. 4,899,271, Specification [C] and JP Patent, Publication of Examined Application B-61-24913 (power source circuit) [D]. Furthermore, JP Patent, Publication of Unexamined Application A-5-284734 discloses a switching power source with a reduced loss in a rectification element, enabling to obtain an improved power conversion efficiency.
However, the aforementioned prior arts have various problems as follows.
The first problem is that in the aforementioned first conventional example, i.e., the piezoelectric transformer of two-terminal output as described in document [A], rectification is carried out by a bridge rectification circuit and accordingly a diode forward voltage drop of 2 VF is caused. If the output voltage is as low as 10 V, a loss is significantly remarkable, lowering the efficiency.
The second problem is that the aforementioned second conventional example, i.e., the piezoelectric transformer having a center tap as disclosed in document [B] requires a production process of a high accuracy for providing the center tap. That is, it is not easy to produce such a configuration and a production cost is increased.
It is therefore an object of the present invention to provide a novel DC/DC converter using a two-terminal piezoelectric transformer of reasonable cost and capable of reducing a rectification circuit loss and enhancing the power conversion efficiency.
In order to achieve the aforementioned object, in the DC/DC converter using a piezoelectric transformer, the rectification-smoothing circuit is realized as a rectification-smoothing circuit using a current doubler.
Furthermore, in the DC/DC converter using a piezoelectric transformer according to the present invention, in order to reduce the loss of the rectification circuit, the diode rectification is replaced by a synchronous rectification. Here, in order to assure drive of the rectification FET (field effect transistor), a gate waveform rectification circuit is used for clamping a piezoelectric transformer output voltage as a sinusoidal wave so as to maintain a constant gate voltage.
According to the present invention, by using a two-terminal output type piezoelectric transformer in combination with a current doubler rectification-smoothing circuit, it is possible to make the diode forward voltage drop VF and to reduce the loss compared to the bridge rectification.
If a synchronous rectification FET is used instead of a diode in the current doubler rectification-smoothing circuit, in a range VF greater than Ioxc2x7Ron (wherein Io is an output current, and Ron is a FET xe2x80x98ONxe2x80x99 resistance), the synchronous rectification FET can reduce the loss more than the diode.
Here, in the present invention, for driving the synchronous rectification FET, a technique is devised to fully utilize a switching power source using a piezoelectric transformer. That is, the piezoelectric transformer has a strong resonance characteristic and accordingly, for any input waveforms (for example, square waveform, triangle waveform, or sinusoidal waveform), the piezoelectric transformer output voltage has a sinusoidal waveform. Consequently, if the piezoelectric transformer output voltage is directly used as a synchronous rectification FET gate signal, the output sinusoidal wave voltage has a peak value exceeding an absolute maximum rating (usually, 20 V) of the synchronous rectification FET gate, which may destroy the synchronous rectification FET. On the contrary, if the piezoelectric transformer output sinusoidal wave voltage has a peak value set to a sufficiently low value not to exceed the gate absolute maximum rating, it becomes impossible to obtain a sufficiently long period of time for exceeding the gate xe2x80x98ONxe2x80x99 voltage threshold value V TH and accordingly, the synchronous rectification FET cannot be in xe2x80x98ONxe2x80x99 state for a sufficiently long period of time.
A solution to this problem is clamping with an appropriate value (such as 10 V) the piezoelectric transformer output sinusoidal wave voltage having a sufficiently great peak value. This can be realized by using a gate waveform rectification circuit.
This enables to overcome the defect that the piezoelectric transformer output voltage is a sinusoidal wave and effectively operate the current doubler rectification-smoothing circuit of synchronous rectification type.